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8143
12-Bit Serial Daisy Chain D/A Converter
Memory
Logic Diagram
FEATURES:
* Microprocessor interfacing in serially controlled systems * Buffered digital output pin for daisy-chaining multiple DACs * Minimizes address-decoding in multiple DAC systems three wire interface for any number of DACs - One data line - One CLK line - One load line * Fast interface timing reduces timing design considerations while minimizing microprocessor wait states. * Improved resistance to ESD * RAD-PAK(R) radiation-hardened against natural space radiation * Total dose hardness: - > 50 Krad (Si), depending upon space mission * Package: - 16 pin RAD-PAK(R) flat pack * Operating temperature: -40 to 85C
DESCRIPTION:
Maxwell Technologies' 8143 is a 12-bit serial-input daisy-chain CMOS digital-to-analog converter (DAC) that features serial data input and buffered serial data output and a greater than 50 krad (Si) total dose tolerance, dependent upon space mission. It was designed for multiple serial DAC systems, where serially daisy-chaining one DAC after another is greatly simplified. The 8143 also minimizes address decoding lines enabling simpler logic interfacing. It allows three-wire interface for any number of DACs: one data line, one CLK line and one load line. Serial data in the input register (MSB first) is sequentially clocked out to the SRO pin as the new data word (MSB first) is simultaneously clocked in from the SRI pin. The strobe inputs are used to clock in/out data on the rising or falling (user selected) strobe edges (STB1, STB2, STB3, STB4). When the shift register's data has been updated, the new data word is transferred to the DAC register with use of LO1 and LD2 inputs. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 50 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.
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12-Bit Serial Daisy-Chain D/A Converter
TABLE 1. 8143 PINOUT DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL IOUT1 IOUT2 AGND STB1 LD1 SRO SRI STB2 LD2 STB3 STB4 DGND CLR VDD VREF RFB Analog Out 1 Analog Out 2 Analog Ground Strobe 1 DAC Register Load 1 Serial Data Out Serial Data In Strobe 2 DAC Register Load 2 Strobe 3 Strobe 4 Digital Groundr DAC Register Clear Positive Supply Voltage Reference Feedback DESCRIPTION
8143
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TABLE 2. 8143 ABSOLUTE MAXIMUM RATINGS
PARAMETER VDD to DGND VREF to DGND VRFB to DGND AGND to DGND DGND to AGND Digital Input Voltage Range Output Voltage (Pin 1, Pin 2) Operating Temperature Range Thermal Impedance Package Weight Storage Temperature Lead Temperature (Soldering, 60 sec) TSTG TL TA SYMBOL MIN --25 -25 ---0.3 -0.3 -40 --65 -MAX 17 25 25 VDD + 0.3 VDD + 0.3 VDD VDD 85 14.13 3 150 300 UNIT V V V V V V V
C C/W
JC
Grams
C C
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12-Bit Serial Daisy-Chain D/A Converter
TABLE 3. 8143 ELECTRICAL CHARACTERISTICS
( VDD = 5V, VREF = 10V; VOUT1 = VOUT2 = VAGND = VDGND = 0V; TA = FULL TEMPERATURE RANGE SPECIFIED UNDER ABSOLUTE MAXIMUM RATINGS, UNLESS OTHERWISE SPECIFIED) PARAMETER STATIC ACCURACY Resolution Nonlinearity Differential Nonlinearity Gain Error 2 Gain Tempco (DGain/DTemp) 3 Power Supply Rejection Ratio (DGain/DVDD) Output Leakage Current 4 Zero Scale Error 5,6 Input Resistance 7 AC PERFORMANCE Output Current Settling Time 3,8 AC Feed through Error (VREF to IOUT1) 3,9 Digital-to-Analog Glitch Energy 3,10 Total Harmonic Distortion 3 Output Noise Voltage Density 3,11 DIGITAL INPUTS/OUTPUTS Digital Input HIGH Digital Input LOW Input Leakage Current Input Capacitance Digital Output High Digital Output Low ANALOG OUTPUTS Output Capacitance 3 Output Capacitance 3 COUT1 Digital Inputs = All 1s COUT2 Digital Inputs = All 0s COUT1 Digital Inputs = All 0s COUT2 Digital Inputs = All 1s
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8143
SYMBOL CONDITIONS
SUBGROUPS
MIN
TYP
MAX
UNIT
N INL DNL GFSE TCGFS PSRR DVDD = 5% ILKG IZSE RIN tS FT Q VREF = 20V p-p @ f = 10 KHz, TA = 25 C VREF = 0V, IOUT load = 100 , CEXT = 13 pF TA = 25 C TA = Full Temperature Range TA = 25 C TA = Full Temperature Range VREF Pin
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2, 3 1 2, 3 1, 2, 3 1, 2, 3 1 1, 2, 3 1, 2, 3 1, 2, 3
12 ---------7 -------
------
-1 1 2 5
Bits LSB LSB LSB ppm/ C %/% nA
0.0006 0.002 --0.002 0.01 11 0.380 -----5 25 0.03 0.15 15 1 2.0 20 --92 13
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LSB k s mV p-p nVs dB nV/Hz
THD VREF = 6V rms @ 1 KHz DAC register loaded with all 1s en 10 Hz to 100 KHz between RFB and IOUT
VIH VIL IIN CIN VOH VOL VIN = 0V to 5V VIN = 0V IOH = -200 A IOL = 1.6 mA
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
2.4 ---4 ------
-----------
-0.8 1 8 -0.4 90 90 60 60
V V A pF V V pF pF
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12-Bit Serial Daisy-Chain D/A Converter
TABLE 3. 8143 ELECTRICAL CHARACTERISTICS
( VDD = 5V, VREF = 10V; VOUT1 = VOUT2 = VAGND = VDGND = 0V; TA = FULL TEMPERATURE RANGE SPECIFIED UNDER ABSOLUTE MAXIMUM RATINGS, UNLESS OTHERWISE SPECIFIED) PARAMETER TIMING CHARACTERISTICS 3 Serial Input to Strobe Setup Times (tSTB = 80 ns) SYMBOL CONDITIONS SUBGROUPS MIN TYP MAX
8143
UNIT
ns tDS1 tDS2 tDS3 tDS4 tDH1 tDH2 STB1 used as the strobe STB2 used as the strobe STB3 used as the strobe TA = 25 C TA = full temperature range STB4 used as the strobe STB1 used as the strobe TA = 25 C TA = full temperature range STB2 used as the strobe TA = 25 C TA = full temperature range STB3 used as the strobe STB4 used as the strobe TA = 25 C TA = full temperature range 9, 10, 11 9, 10, 11 9 10, 11 9, 10, 11 9 10, 11 9 10, 11 9, 10, 11 9, 10, 11 9 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TA = 25 C TA = temperature range 9 10, 11 9, 10, 11 9, 10, 11 1, 2, 3 All digital inputs = 0V or VDD All digital inputs = VIH or VIL Digital inputs = 0V or VDD, Digital inputs = VIH or VIL, 1, 2, 3 1, 2, 3 50 20 10 20 20 40 50 50 60 80 80 --100 80 80 80 80 140 180 0 80 4.75 --------------------------5 --------------
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Serial Input to Strobe Hold Times (tSTB = 80 ns) STB to SRO Propagation Delay 13 SRI Data Pulsewidth STB1 Pulsewidth (STB1 = 80 ns) STB3 Pulsewidth (STB3 = 80 ns) STB4 Pulsewidth (STB4 = 80 ns) Load Pulsewidth LSB Strobe into Input Register to Load DAC Register Time CLR Pulsewidth Supply Voltage Supply Current Power Dissipation 1. 2. 3. 4. 5.
14
ns tDH3 tDH4 tPD tSRI tSTB1 tSTB2 tSTB3 tSTB4 tLD1, tLD2 tASB tCLR VDD IDD PD --220 300 ---------5.25 0.1 2 0.5 10 ns ns ns ns ns ns ns ns ns V mA mW
STB2 Pulsewidth (STB2 = 100 ns)
POWER SUPPLY CHARACTERISTICS
All grades are monotonic to 12 bits over temperature. Using internal feedback resistor. Guaranteed by design and not tested. Applies to IOUT; all digital inputs = VIL, VREF = 10V; specification also applied for IOUT2 when all digital inputs = VIH. VREF = 10V, all digital inputs = 0V.
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12-Bit Serial Daisy-Chain D/A Converter
8143
6. Calculated from worst case RREF: IZSE (in LSBs) = (RREF x ILKG x 4096)/VREF. 7. Absolute temperature coefficient is less than 300 ppm/ C. 8. IOUT, Load = 100 . CEXT = 13 pF, digital input = 0V to VDD or VDD to 0V. Extrapolated to 1/2 LSB: ts = propagation delay (tPD) + 9t, where t equals measured time constant of the final RC decay. 9. All digital inputs = 0V. 10.VREF = 0V, all digital inputs = 0V to VDD or VDD to 0V. 11. Calculations from en = sqrt(4K* T*R*B) where: K = Boltzmann constant ((J/K) = 1.38E-23 Juoles/Kelvin), R = resistance (10K for the 8143) T = resistor temperature (Kelvin 26C ~ 300K), R = bandwidth, Hz 12.Digital input are CMOS gates; IIN typically 1 nA at +25 C. 13.Measured from active strobe edge (STB) to new data output at SRO; CL = 50 pF. 14.Minimum low time pulsewidth for STB1, STB2, and STB4, and minimum high time pulsewidth for STB3.
FIGURE 1. MULTIPLE WITH THREE-WIRE INTERFACE
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 2. MULTIPLYING MODE FREQUENCY RESPONSE VS. DIGITAL CODE
8143
FIGURE 3. MULTIPLYING MODE TOTAL HARMONIC DISTORTION VS. FREQUENCY
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 4. SUPPLY CURRENT VS. LOGIC INPUT VOLTAGE
8143
FIGURE 5. LINEARITY ERROR VS. DIGITAL CODE
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 6. LINEARITY ERROR VS. REFERENCE VOLTAGE
8143
FIGURE 7. LOGIC THRESHOLD VOLTAGE VS. SUPPLY VOLTAGE
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FIGURE 8. DNL ERROR VS. REFERENCE VOLTAGE
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 9. DIGITAL OUTPUT VOLTAGE VS. OUTPUT CURRENT
8143
Definition of Specifications The resolution of a DAC is the number of states (2n) into which the full-scale range (FSR) is divided (or resolved), where "n" is equal to the number of bits. Settling Time Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stimulus; i.e., zero to full-scale. Gain Ratio of the DAC's external operational amplifier output voltage to the VREF input voltage when all digital inputs are HIGH. Feedthrough Error Error caused by capacitive coupling from VREF to output. Feedthrough error limits are specified with all switches off. Output Capacitance Capacitance from IOUT1 to ground. Output Leakage Current Current appearing at IOUT1 when all digital inputs are LOW, or at IOUT2 terminal when all inputs are HIGH. General Circuit Information The 8143 is a 12-bit serial-input, buffered serial-output, multiplying CMOS D/A converter. It has an R-2R resistor ladder network, a 12-bit input sift register, 12-bit DAC register, control logic circuitry, and a buffered digital output stage. The control logic forms an interface in which serial data is loaded, under microprocessor control, into the input sift register and then transferred, in parallel, to the DAC register. In addition, buffered serial output data is present at the SRO pin when input data is loaded into the input register. This buffered data follows the digital input data (SRI) by 12 clock cycles and is available for daisy-chaining additional DACs.
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12-Bit Serial Daisy-Chain D/A Converter
8143
An asynchronous CLEAR function allows resetting the DAC register to a zero code (0000 0000 0000) without altering data stored in the registers. A simplified circuit of the 8143 is shown in Figure 10. An inverses R-2R ladder network consisting of silicon-chrome, thin-film resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either IOUT1 or IOUT2. Switching current to IOUT1 or IOUT2 yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R (typically 11 k). The VREF input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the Absolute Maximum Ratings chart. The twelve output current-steering switches are in series with the R-2R resistor ladder, and therefore, can introduce bit errors. It was essential to design these switches such that the switch "ON" resistance by binarily scaled so that the voltage drop across each switch remains constant. If, for example, Switch 1 of Figure 10 was designed with an "ON" resistance of 10 , Switch 2 for 20 , etc., a constant 5 mV drop would then be maintained across each switch. To further ensure accuracy across the full temperature range, permanently "ON" MOS switches were included in series with the feedback resistor and the R-2R ladder's terminating resistor. The Simplified DAC Circuit, Figure 10, shows the location of these switches. These series switches are equivalently scaled to two times Switch 1 (MSB) and top Switch 12 (LSB) to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn "ON" these serial switches.
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FIGURE 10. SIMPLIFIED DAC CIRCUIT
ESD Protection The 8143 digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 11 shows the input protection diodes. High voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions.
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 11. DIGITAL INPUT PROTECTION
8143
Equivalent Circuit Analysis Figures 12 and 13 show equivalent circuits for the 8143 internal DAC with all bits LOW and HIGH, respectively. The reference current is switched to IOUT2 when all data bits are LOW, and to IOUT1 when all bits are HIGH. The ILEAKAGE current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the constant 1-bit current drain, through the ladder's terminating resistor. Output capacitance is dependent upon the digital input code. This is because the capacitance of a MOS transistor changes with applied gate voltage. This output capacitance varies between the low and high values.
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FIGURE 12. EQUIVALENT CIRCUIT (ALL INPUTS LOW)
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 13. EQUIVALENT CIRCUIT (ALL INPUT HIGH)
8143
Dynamic Performance
Analog Output Impedance The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT1 terminal, varies between 11 kW (the feedback resistor alone when all digital input are LOW) and 7.5 k (the feedback resistor in parallel with approximately 30 k of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the 8143. The use of a small compensation capacitor may be required when high speed operational amplifier's feedback resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high speed amplifiers are: 1. Phase compensation (see Figures 16 and 17). 2. Power supply decoupling at the device socket and use of proper grounding techniques. Output Amplifier Considerations When using high speed op amps, a small feedback capacitor (typically 5 pF-30 pF) should be used across the amplifiers to minimize overshoot and ringing. For low speed or static applications, ac specification of the amplifier are not very critical. In high speed applications, slew rate, settling time, open-loop gain and gain/phase margin specifications of the amplifier should be selected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier's noninverting input terminal. This resistor should not be used. Instead, the amplifier should have a bias current that is low over the temperature range of interest. Static accuracy is affected by the variation in the DAC's output resistance. This variation is best illustrated by using the circuit of Figure 14 and the equation:
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 14. SIMPLIFIED CIRCUIT
8143
Where RO is a function of the digital code, and: RO = 10 k for more than four bits of Logic 1, RO = 30 k for any single bit of Logic 1.
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Therefore, the offset gain varies as follows: at code 0011 1111 1111,
at code 0100 0000 0000,
The error difference is 2/3 VOS. Since one LSB has a weight (for VREF = 10V) of 2.4 mV for the 8143, it is clearly important that VOS be minimized, using either the amplifier's pulling pins, an external pulling network, or by selection of an amplifier with inherently low VOS. Amplifiers with sufficiently low VOS include OP77, OP07 and OP27. Interface Logic Operation The microprocessor interface of the 8143 has been designed with multiple STROBE and LOAD inputs to maximize interfacing options. Control signals decoding may be done on chip or with the use of external decoding circuitry (see Figure 21). Serial data is clocked into the input register and buffered output stage with STB1, STB2, or STB4. The strobe inputs are active on the rising edge. STB3 may be used with a falling edge clock data. Serial data output (SRO) follows the serial data input (SRI) by 12 clocked bits. Holding any STROBE input at its selected state (i.e., STB1, STB2, or STB4 at logic HIGH or STB3 at logic LOW) will act to prevent any further data input. When a new data word has been entered into the input register, it is transferred to the DAC register by asserting both LOAD inputs.
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8143
The CLR input allows asynchronous resetting of the DAC register to 0000 0000 0000. This reset does not affect data held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to 0V. In bipolar mode, the output will go to -VREF. Interface Input Description STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11) - Input register and buffered output strobe. Inputs active on falling edge. Selected to load serial data into input register and buffered output stage. See Table 3 for details. STB3 (Pin 10) - Input register and buffered output strobe input. Active on falling edge. Selected to load serial data into input register and buffered output stage. See Table 3 for details. LD1 (Pin 5), LD2 (Pin 9) - Load DAC register inputs. Active low. Selected together to load contents of input register into DAC register. CLR (Pin 13) - Clear input. Active low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000 0000 0000) regardless of other interface inputs.
FIGURE 15. TIMING DIAGRAM
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* Strobe waveform is inverted if STB3 is used to strobe serial data bits into input register. ** Data is strobed into and out of the input shift register MSB first.
TABLE 1. TRUTH TABLE
INPUT REGISTER/DIGITAL OUTPUT STB4 0 0 0 STB3 1 1 1 CONTROL INPUTS STB2 0 0 0 0 0 0 STB1 DAC REGISTER CLR X X X X CONTROL INPUT LD2 X X X X LD1 X X X X Serial data bit loaded from SRI into input register and digital output (SRO pin) after 12 clocked bits
1,2
OPERATION
NOTES
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12-Bit Serial Daisy-Chain D/A Converter
TABLE 1. TRUTH TABLE
INPUT REGISTER/DIGITAL OUTPUT STB4 1 X X X STB3 X 0 X X CONTROL INPUTS STB2 X X 1 X STB1 X X X 1 0 X X DAC REGISTER CLR CONTROL INPUT LD2 LD1 OPERATION
8143
NOTES
No operation (input register and SRO)
2
Reset DAC register to zero code (Code: 0000 0000 0000) Asynchronous operations) No operation (DAC register and SRO) Load DAC register with the contents of input register
2 ,3
1 1 1
1 X 0
X 1 0
2
2
1. Serial data is loaded into Input Register MSB first, on edges shown. is positive edges, is negative edge. 2. 0 = Logic LOW, 1 = Logic HIGH, X = Don't care.
3. CLR = 0 asynchronously resets DAC register to 0000 0000 0000, but has no effect on Input Register.
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Applications Information
Unipolar Operation (2-Quadrant) The circuit shown in Figures 16 and 17 may be used with an ac or dc reference voltage. The circuit's output will range between 0V and 10V (4095/4096) depending upon the digital input and the analog output is shown in Table 4. The VREF voltage range is the maximum input voltage range of the op amp or 25V, whichever is lowest.
TABLE 4. UNIPOLAR CODE TABLE1,2
DIGITAL INPUT MSBLSB 111111111111 100000000001 100000000000 011111111111 000000000001 NOMINAL ANALOG OUTPUT (VOUT AS SHOWN IN FIGURES 16 AND 17) -VREF (4095/4096) -VREF (2049/4096) -VREF (2048/4096) = -VREF/2 -VREF (2047/4096) -VREF (1/4096)
000000000000 -VREF (0/4096) = 0 1. Nominal full scale for the circuits of Figures 16 and 17 is given by FS = -VREF (4095/4096) 2. Nominal LSB magnitude for the circuit of Figure 16 and 17 is given by LSB = VREF(1/4096) or VREF(2-N).
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 16. UNIPOLAR OPERATION WITH HIGH ACCURACY OP AMP (2-QUADRANT)
8143
FIGURE 17. UNIPOLAR OPERATION WITH FAST OP AMP AND GAIN ERROR TRIMMING (2-QUADRANT)
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In many applications, the 8143 zero scale error and low gain error, permit the elimination of external trimming components without adverse effects on circuit performance. For applications requiring a tighter gain error than 0.024% at 25 C for the top grade part, or 0.048% for the lower grade part, the circuit in Figure 17 may be used. Gain error may be trimmed by adjusting R1. The DAC register must first be loaded with all 1s. R1 is then adjusted until VOUT = -VREF (4095/4096). In the case of an adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF adjusted to yield the desired full-scale output. Bipolar Operation (4-Quadrant) Figure 18 details a suggested circuit for bipolar, or offset binary, operation. Table 5 shows the digital input-to-analog output relationship. The circuit uses offset binary coding. Twos complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. Resistor R3, R4 and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. Mismatching between R3 and R4 causes offset and full-scale error. Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting the ratio of R3 to R4 to yield VOUT = 0V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and adjusting either the amplitude of VREF of the value of R5 until the desired VOUT is achieved.
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12-Bit Serial Daisy-Chain D/A Converter
TABLE 5. BIPOLAR (OFFSET BINARY) CODE TABLE
DIGITAL INPUT MSBLSB 1 1 1 11 1 1 11 1 1 1 1 0 0 00 0 0 00 0 0 1 1 0 0 0 0 0 0 00 0 0 0 0 1 1 11 1 1 11 1 1 1 0 0 0 00 0 0 00 0 0 1 0 0 0 00 0 0 00 0 0 0 NOMINAL ANALOG OUTPUT (VOUT AS SHOWN IN FIGURE 18) VREF (2047/2048) VREF (1/2048) 0 -VREF (1/2048) -VREF (2047/2048) -VREF (2048/2048)
8143
Daisy-Chaining 8143 Many applications use multiple serial input DACs that use numerous interconnecting lines for address decoding and data lines. In addition, they use some type of buffering to reduce loading on the bus. The 8143 is ideal for just such an application. It not only reduces the number of interconnecting lines, but also reduces bus loading. The 8143 can be daisy-chained with only three lines: one data line, one CLK and one load line, see Figure 19.
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FIGURE 18. BIPOLAR OPERATION (4-QUADRANT, OFFSET BINARY)
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 19. MULTIPLE 8143S WITH THREE WIRE INTERFACE
8143
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Analog/Digital Division The transfer function for the 8143 connect is the multiplying mode as shown in Figures 16 and 17 is:
where AX assumes a value of 1 for an "ON" bit and 0 for an "OFF" bit. The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 20 and is:
The above transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits "OFF" since division by zero is infinity. With all bits "ON", the gain is 1 (1 LSB). The gain becomes 4096 with the LSB, Bit 12, "ON".
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 20. ANALOG/DIGITAL DIVIDER
8143
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Application Tips In most applications, linearity depends on the potential of IOUT1, IOUT2, and AGND (Pins 1, 2 and 3) being exactly equal to each other. In most applications, the DAC is connected to an external Op Amp with its noninverting input tied to ground (see Figures 16 and 17). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier's input offset voltage should be nulled to less than 200 V (less than 10% of 1 LSB). The operational amplifier's noninverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The VDD power supply should have a low noise level with no transients greater than 17V. It is recommended that the digital input be taken to ground or VDD via a high value (1 M) resistor, this will prevent the accumulation of static charge if the PC card is disconnected from the system. Peak supply current flows as the digital input pass through the transition region (see Figure 4). The supply current decreases as the input voltage approaches the supply rails (VDD or DGND), i.e., rapidly slewing logic signals that settle very near the supply rails will minimize supply current. Interfacing to the MC6800 As shown in Figure, the 8143 may be interfaced to the 6800 by successively executing memory WRITE instruction while manipulating the data between WRITEs, so that each WRITE presents the next bit. In this example, the most significant bits are found in memory locations 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB7 line. The serial data loading is triggered by STB4 which is asserted by a decoded memory WRITE to a memory location, R/ W, and f2. A WRITE to another address location transfers data from input register to DAC register.
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 21. MC6800 INTERFACE
8143
Interface to the 8085 The 8143's interface to the 8085 microprocessor is shown in Figure 22. Note that the microprocessor's SOD line is used to present data serially to the DAC. Data is strobed into the 8143 by executing memory write instructions. The strobe 2 input is generated by decoding an address location and WR. Data is loaded into the DAC register with a memory write instruction to another address location. Serial data supplied to the 8143 must be present in the right-justified format in registers H and L of the microprocessor.
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FIGURE 22. 8085 INTERFACE
Interface to the 68000 Figure 23 shows the 8143 configured to the 68000 microprocessor. Serial data input is similar to that of the 6800 in Figure 21.
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12-Bit Serial Daisy-Chain D/A Converter
FIGURE 23. 8143 TO 68000 P INTERFACE
8143
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12-Bit Serial Daisy-Chain D/A Converter
8143
Memory
16 PIN RAD-PAK(R) FLAT PACKAGE
SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.325 0.020 0.005 0.115 0.015 0.004 0.407 0.275 -0.150 0.030 DIMENSION NOM 0.135 0.017 0.005 0.415 0.280 -0.156 0.062 0.050 BSC 0.335 0.033 0.024 16 0.345 0.045 0.045 MAX 0.150 0.019 0.007 0.423 0.285 0.500 0.162 --
F16-01 Note: All Dimensions in inches
07.23.03 REV 3
All data sheets are subject to change without notice
22
(c)2003 Maxwell Technologies. All rights reserved.
12-Bit Serial Daisy-Chain D/A Converter
Important Notice:
8143
These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.
Memory
07.23.03 REV 3
All data sheets are subject to change without notice
23
(c)2003 Maxwell Technologies. All rights reserved.
12-Bit Serial Daisy-Chain D/A Converter
Product Ordering Options
8143
Model Number 8143 RP F X Feature Option Details
Screening Flow
Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25C) I = Industrial (testing @ -40C, +25C, +85C)
Memory
Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK(R) package
Base Product Nomenclature
12-Bit Serial Daisy Chain D/A Converter
07.23.03 REV 3
All data sheets are subject to change without notice
24
(c)2003 Maxwell Technologies. All rights reserved.

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